| Leaving UPSET |
| quit |
Quit UPSET tool |
| Import Files |
| load_lef |
Load LEF technology file |
| load_lib |
Load LIB Timing Library file |
| load_verilog |
Load Verilog netlist |
| load_spef |
Load parasitics SPEF file |
| load_saif / read_saif |
Load Switching Activity (SAIF) file |
| Tool Configuration |
| set_timing_model |
Select timing model |
| set_timing_RC_mode |
Select interconnect timing model |
| Set Simulation Parameters |
| set_spice_simulation_parameters |
Set SPICE simulation parameters |
| SDC Constraints |
| create_clock |
Create clock |
| set_input_delay |
Set design input delay constraint |
| set_output_delay |
Set design output delay constraint |
| Static Timing Analysis |
| report_timing |
Perform STA |
| Components Legalisation |
| legalise_components |
Legalise the components of the circuit removing overlaps and aligning components to power rails |
| Simulation |
| set_net_supply |
Create a SPICE supply |
| simulate_net |
Perform SPICE simulation |
| SET Generation |
| generate_SET_glitch |
Generate SET glitch and report rise and fall edges slew and arrivals |
| create_particle_profile |
Create a particle profile |
| delete_particle_profile |
Delete specified particle profile |
| clear_particle_profiles_info |
Clear all particle profiles information |
| list_particle_profiles |
List all particle profiles info |
| list_cubes_propagating_input_SETs_to_output |
List all cubes propagating input SETs to output |
| create_SET_scenario |
Create a SET scenario |
| load_SET_scenarios |
Load SET scenario file |
| list_SET_scenarios |
List specified SET scenario information |
| list_SET_scenarios |
List all stored SET scenarios information |
| clear_SET_scenarios |
Remove all stored SET scenarios |
| generate_SET_scenario_glitch |
Generate SET glitch for the specified scenario or all scenarios loaded in memory |
| set_SET_generation_parameters |
Set SET generation model. For BIAS model capacitance Cs, Recombination Currents and Fermi constants parameters can be specified |
| generate_SET_scenario_custom_glitch |
Generate SET glitch scenario as a PWL voltage waveform for the specified receive gatepin |
| Nodes Measurements |
| create_net_spice_probe |
Create a SPICE probe for the specified net |
| plot_spice_probe |
Plot the specified probe data |
| SET Propagation |
| propagate_SET_glitch |
Propagate SET glitch and report measurements |
| propagate_SET_scenario_glitch |
Propagate SET glitch for the specified scenario or all scenarios loaded in memory |
| set_SET_glitch_propagation_mode |
Set SET glitch propagation mode. "Vanilla" mode is represented as 0, Detailed TimeStamp-based as 1, and Bounded TimeStamp-based as 2 |
| set_SET_analysis_mode |
Set SET analysis mode. Vector-based is represented as 0, and Probabilistic as 1 |
| perform_SET_analysis |
Perform fast SET analysis for the specified gatepins or all gatepins loaded in memory |
| perform_exhaustive_SET_analysis |
Perform exhaustive SET analysis, i.e. for all circuit gatepins and particle profiles combinations |
| Logical Masking |
| create_SET_scenario_case_analysis |
Create SET scenario case analysis |
| list_SET_scenario_case_analysis |
List SET scenario case analysis information |
| clear_SET_scenario_case_analysis |
Remove SET scenario case analysis information |
| Static Probabilities |
| list_saif_info |
List SAIF information |
| set_static_probability |
Set the static probability value for the specified gatepin(s) |
| reset_static_probabilities |
Reset static probabilities |
| list_static_probabilities |
Propagate and list static probabilities stored in memory |
| Component Sensitivity Metrics |
| list_gatepin_set_analysis_info |
List SET analysis information for the specified gatepin |
| list_all_gatepin_set_analysis_info |
List SET analysis information for all gatepins |
| report_SET_scenario_timingpoints |
Report SET scenario timingpoints |
| report_SET_generation_probabilities |
Report SET generation probabilities for all gatepins |
| ECO SET Mitigation Techniques |
| eco_swap_component_pins |
Rewire two input pins of a component |
| eco_upsize_component |
Upsize a component to the immediate larger component |
| eco_downsize_component |
Downsize a component to the immediate smaller component |
| eco_charge_sharing |
Insert charge-sharing logic to a target gatepin |
| eco_fanout_decomposition |
Perform fan-out decomposition in a target component |
| eco_tmr_component |
Apply Triple Modular Redundancy (TMR) to a target component |
| eco_insert_filter |
Insert a SET filter to a target gatepin |
| eco_insert_cascaded_inverter |
Insert a pair of cascaded inverters to a target gatepin |